The present invention relates generally to the field of memory devices and more specifically to the field of nonvolatile memory devices containing diode steering elements.
Nonvolatile memory arrays maintain their data even when power to the device is turned off. In one-time-programmable arrays, each memory cell is formed in an initial unprogrammed state, and can be converted to a programmed state. This change is permanent, and such cells are not erasable. In other types of memories, the memory cells are erasable, and can be rewritten many times.
Cells may also vary in the number of data states each cell can achieve. A data state may be stored by altering some characteristic of the cell which can be detected, such as current flowing through the cell under a given applied voltage or the threshold voltage of a transistor within the cell. A data state is a distinct value of the cell, such as a data ‘0’ or a data ‘1’. In a one diode, one resistivity switching material memory cell, the state of the memory cell is programmed by biasing the diode. In particular, polysilicon diodes can be used.
Referring to FIG. 1, a side view of a prior art diode 105 of a memory cell is shown. The diode 105 can be a p-i-n diode including a p-type semiconductor region 110, an i-type semiconductor region 130, and a n-type semiconductor region 150. The diode 105 is connected in series with a storage element 170, such as a resistivity switching material. The storage element 170 can be above or below the diode 105. In a three-dimensional architecture, the diode 105 is typically vertically oriented. The diode 105 and the storage element 170 are electrically connected between a bit line 190 and a word line 195. The diode 105 suffers a high reverse leakage and a low forward current, especially where the diode 105 is a polysilicon diode.
Referring to FIG. 2, a side view of a prior art diode with oxide barriers 205 of a memory cell is shown. The diode with oxide barriers 205 can be a p-i-n diode including a p-type semiconductor region 210, an i-type semiconductor region 230, and a n-type semiconductor region 250. A first oxide 220 is located at the interface between the p-type semiconductor region 210 and the i-type semiconductor region 230. A second oxide 240 is located at the interface between the i-type semiconductor region 230 and the n-type semiconductor region 250. The first oxide 220 and the second oxide 240 can be, for example, a rapid thermal oxide (RTO) or a native oxide. The diode with oxide barriers 205 is connected in series with a storage element 170, such as a resistivity switching material. The storage element 170 can be above or below the diode with oxide barriers 205. In a three-dimensional architecture, the diode with oxide barriers 205 is typically vertically oriented. The diode with oxide barriers 205 and the storage element 170 are electrically connected between a bit line 190 and a word line 195.
Referring to FIG. 3, a graph of a doping profile of the prior art diode with oxide barriers of FIG. 2 is shown. The graph shows the doping concentration (atoms/cm3) versus the depth (nm) from the top of the diode with oxide barriers 205. Plot 310 shows the doping concentration of boron (atomic weight 11). Plot 320 shows the doping concentration of phosphorous. The first oxide 220 and the second oxide 240 prevent doping diffusion (i.e. of the boron and phosphorous) and enlarges the i-type semiconductor region 230. In this example, the i-type semiconductor region 230 is about 36 nm (i.e. approximately between 24 nm and 60 nm in FIG. 3). In a similar diode without oxide barriers a 27 nm intrinsic region (5×1017 per cm3 as the intrinsic doping) would be expected.
Referring to FIG. 4, a current-voltage (I-V) graph of the prior art diode with oxide barriers of FIG. 2 and a diode without oxide barriers operating at room temperature (RT) is shown. The graph shows current (A) versus voltage (V) for devices created on four separate wafers. Plot 410 shows the I-V graph for a diode without oxide barriers created on wafer 1 (W1). Plot 420 shows the I-V graph for a diode without oxide barriers created on wafer 2 (W2). Plot 430 shows the I-V graph for a diode with oxide barriers created on wafer 3 (W3). Plot 440 shows the I-V graph for a diode with oxide barriers created on wafer 4 (W4). The diodes on all four wafers are comparable. At room temperature and at 2.0V, the forward current of the diode without oxide barriers is approximately two times the forward current of the diode with oxide barriers. At room temperature and at 4.5V, the reverse leakage current of the diode without oxide barriers is 3.5 times the reverse leakage current of the diode with oxide barriers. Therefore, the reverse leakage is reduced. However, the first oxide 220 and the second oxide 240 reduce the forward current.
Referring to FIG. 5, a current-voltage (I-V) graph of the prior art diode with oxide barriers of FIG. 2 and a diode without oxide barriers operating at high temperature (HT) is shown. The graph shows current (A) versus voltage (V) for devices created on four separate wafers. The Plot 510 shows the I-V graph for a diode without oxide barriers created on wafer 1 (W1). Plot 520 shows the I-V graph for a diode without oxide barriers created on wafer 2 (W2). Plot 530 shows the I-V graph for a diode with oxide barriers created on wafer 3 (W3). Plot 540 shows the I-V graph for a diode with oxide barriers created on wafer 4 (W4). The diodes on all four wafers are comparable. At high temperature and at 2.0V, the forward current of the diode without oxide barriers is approximately two times the forward current of the diode with oxide barriers. At high temperature and at 4.5V, the reverse leakage current of the diode without oxide barriers is 1.3 times the reverse leakage current of the diode with oxide barriers. Therefore, the reverse leakage is reduced. However, the first oxide 220 and the second oxide 240 reduce the forward current.
In addition to the reduction in the forward current, RTO grown oxide needs a relatively high popping voltage to break down the thin oxide layer. Since the popping voltage needs to be so high, it causes the diode with oxide barriers to be less unreliable. An intentionally designed native oxide can be an oxide barrier without having a popping event. However, the benefit of reverse leakage reduction is reduced at high temperature due to the impurity introduced by the native oxide layer through high temperature anneal.